Field of the Present Disclosure
The present disclosure relates to a multi-layer capacitor package and a housing thereof, and, more particularly, to a multi-layer capacitor package where a multi-layer capacitor with a high level capacitance and stable structure is packaged in a package housing, and to a housing thereof.
Discussion of the Related Art
The capacitor includes, in a simplest form, two electrodes and a dielectric layer therebetween. When a voltage is applied to the capacitor, a positive charge is induced at one electrode and a negative charge is induced at the other electrode. Thus, electrical attraction may be generated therebetween. The positive and negative charges are accumulated to reserve energy. Recently, a single capacitor may include at least three vertical alterations of electrodes and dielectric layers. This may be referred to as a multi-layer capacitor which is used on demand of a smaller device or high-power device.
The multi-layer capacitor may have parallel connections of the electrodes. In order to apply the voltage thereto, it is necessary that the areas of the electrodes decrease from a bottom silicon substrate to a top portion of the capacitor. That is, this area decrease may cause a lowered efficiency of the multi-layer capacitor. In this configuration, formation of the external terminals to allow the parallel connections of the electrodes may lead to damage of the bottom electrode due to an external force.